The large integration of semiconductor ICs has been accomplished by a reduction in individual device size. With this reduction of device size, many challenges arise in the manufacture of the ICs. Each device requires interconnections for exchanging electrical signals from one device to another device. Using the DRAM as an example, the word line and the bit line for a memory cell serve as interconnections. Connections between metal layers are constructed by filling a conductive plug in a via hole formed in an isolation layer. The conductive material chosen for the contact must have a low work function as well as a low electron resistivity. Aluminum, tungsten, titanium and copper are candidates for the contact metal material. The technology of forming effective contacts have met obstacles due to miniaturization of the device to sub-micron range. The advanced method to form the contact is the use of the tungsten plug technique. In short, the tungsten is filled in a contact hole in a dielectric layer. The tungsten features the benefit of low resistivity and can be formed at a temperature lower than 500 degrees centigrade by chemical vapor deposition.
Typically, a planarizaion process is needed after the PMD (pre-metal dielectric) layer is formed. A. Tissier has mentioned many methods of planarizaion for pre-metal and metal level layer in "Proceeding on Advanced Metallization for ULSI Application", p.341, 1994. The BPSG film has been widely used as the pre-metal dielectric (PMD) to achieve global planarization for advanced ULSI devices. However, the high temperature anneal that is performed after opening the contact hole will induce the BPSG film to re-flow, thus an overhang structure will be generated at the top of the contact hole. The issue has been mentioned in U.S. Pat. No. 5,554,565. In U.S. Pat. No. 5,364,817, a method is disclosed to provide an effective method of metallization with improved step coverage and reduced electromigration problem.
A further prior method may cause a void in a conductive layer due to bad step coverage. The general processes become more challenging as the spacing between the metal interconnections further shrink. A void may often be formed between the interconnections. Thus, what is required is a void-free method for making the interconnection.